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Weekly Column

Repeal Denied: MST will help extend Moore's Law for another 15 years.

Status: [CLOSED] comments (83)
By Robert X. Cringely

When will Moore's Law be repealed? For the 30+ years I have been in and around the computer industry I have heard that question asked. The reason is obvious: this seemingly magical doubling of computing power per dollar every 18 months has been taking place since the early 1960s and surely has to stop sometime, right? Not yet, it doesn't. Thanks to some clever new ways of making CMOS chips, it looks like Moore's Law will remain in effect for at least another 15 years. This week's column is my attempt to explain why this is so and to give some idea what it means to us all.

Cranky writer's note: this column has a global audience that includes high school kids and Nobel laureates. From time to time in columns like this one I attempt to explain technical issues in broad terms that are understandable by most readers. This inevitably means that some readers (you know who you are) will think the content is simplistic, obvious, already well known to everyone in your PhD program, or simply stupid. Much as it might surprise you, I can live with this and hope that you can, too.

Now back to Moore's Law.

We used to think what would repeal Moore's Law was the simple inability of photolithography to etch ever thinner lines on each silicon wafer. Now that we are well into nanometer feature sizes, though, it is clear that problem has been solved. What hurts us today is heat. The smaller they get the hotter our chips run. So we end up either with elaborate cooling systems or deliberately hobbled performance, or a little of both.

Today's move to dual- and multi-core processors is in direct response to nothing more than the need to effectively increase die size to keep temperatures down. Multi-core chips can also be run at lower clock speeds to keep down heat while relying on more than one core to recover from this apparent performance disadvantage.

This is, of course, in complete defiance of conventional chip company marketing, which says that the smaller you make a chip the less power it consumes and the lower voltage it requires -- that multi-cores are simply multo-fast. However the truth is that lower voltages tend to be a requirement for keeping CPU temperatures down as much as anything and multiple cores are often just a way of gaining increased heat sink area.

This extra chip heat comes generally from four sources. The first is simply reduced surface area; yes the voltage is lower, but if the ratio of old voltage to new voltage is less than the ratio of old surface area to new surface area from the previous product generation and manufacturing process, well then the chip simply has to get hotter, since it is dramatically smaller yet doing the same work. Voltages drop linearly while surface areas decrease as a far more rapid square function.

The second reason chips -- especially microprocessors -- are getting hotter is the demands of keeping various clocks in sync. Using synchronous logic, some significant percentage of transistors is required simply to keep all the clock signals aligned on a 400 million transistor chip. Asynchronous -- clockless -- logic can do away with the need for that extra, power-wasting circuitry, as I wrote about in this space many years ago (it's in this week's links). As such companies including Sun and Intel are trying to make more and more of their chip circuitry asynchronous, but that is a long and crooked path toward chips that consume no power at all in the milliseconds they aren't being used.

But the greatest producers of heat are relatively new on the scene: two forms of current leakage that are especially prevalent at feature sizes substantially below 100 nanometers. The smaller we go the tougher it gets.

The first type of current leakage is called "gate leakage," which is a quantum effect in which electrons mysteriously migrate through materials they aren't supposed to be migrating through. Gate leakage is active, meaning it takes place only when the chip is actually running. Any leakage consumes power and creates heat without doing usable work, so of course we hate it unless, like I did with my old PDP-8, you are relying on your computer to heat your house.

The other form of leakage is called "sub-threshold" and actually takes place when the chip ISN'T doing any work, when it is off. Sub-threshold leakage is generally attributed to very thin layers that don't do a very good job of insulating, as they are SEMI-conductors.

The big problem with gate leakage is that it doesn't scale. You can make the chips smaller by going to a new manufacturing process (from 65 nanometers down to 45 nanometers, for example) and everything scales down EXCEPT the gate leakage, which remains about the same for similar voltages. Since the gate leakage is the same but the chips are a lot smaller, well you can see the problem, which is why you need that liquid cooling system on your over-clocked game PC.

For 45 nanometer processors these two forms of current leakage consume 70 percent of the power used to run the chips. That is unless you do something to reduce the gate leakage. There have been a variety of techniques used to reduce gate leakage and the best known are "strained silicon," in which the gates are put under compression or tension that somehow inhibits leakage; Silicon-on-Insulator (SOI), in which an insulating layer under the silicon inhibits current leakage and high-K (usually hafnium) metal gates, which are less prone to current leakage. If you are a chip designer intent on reducing gate leakage, you ultimately use all three of these techniques in the order I have presented them because that is from least- to most-expensive.

Intel's new Penryn family of 45 nanometer processors announced at the end of last year uses all three techniques.

But there is a new technique on the block for reducing gate leakage from British inventor Robert Mears, best known for leading the team that developed the erbium doped fiber amplifier that has allowed in situ fiber-optic cables to massively increase their ability to carry data by simultaneously using multiple wavelengths of light to carry parallel data streams. This guy made today's Internet possible. Mears has been working since 2001 on Mears Silicon Technology (MST), which is a new kind of semiconductor coating with unique and tunable qualities.

In one sense MST is like Silicon-on-Insulator in that it is a special layer laid down on the entire silicon wafer before further processing. But where SOI solely inhibits leakage down through the underlying insulator layer, the custom MST layer does that and more. MST inhibits vertical current flow where you don't want it and improves current flow in the horizontal plane where you need it for higher performance. And unlike high-K gates, MST is cheap to implement, requiring no exotic materials or new manufacturing equipment. Using MST alone, the two forms of gate leakage can be reduced by 60 to 80 percent while also making the chips run faster. The result is faster, cheaper chips that consume less energy and run cooler.

As always I am too stupid to own stock in Mears Technologies or any of the other companies I write about.

Just because you use MST doesn't mean you can't also use strained silicon, silicon-on-insulator, or high-K gates. This new technology is just another tool for modern process engineers and can be used in any combination to fine-tune performance, energy consumption, or both.

As CMOS fabrication processes get ever smaller (Intel is right now sampling 32 nanometer processors), it becomes possible to use a new gimmick called Thin Field Effect Transistors (Thin FETs), effectively 3-D transistors, which can further reduce the real estate of each transistor. And with a billion transistors on a chip, that size reduction, which goes beyond the traditional feature reduction, can lead to yet further performance improvements. But the problem with Thin FETs is they are difficult to strain, so current leakage goes back up again. Fortunately, according to Mears Technologies, MST works well in 3-D and can save the day for Thin FETs, which we'll see in 32 and 22 nanometer chips coming in the next 3 to 7 years.

But wait there's more! Take the process down to below 10 nanometers and MST can be used for devices using spintronics, where the gate action is based on the controllable spin of a single electron that can be polarized one way or another to either allow or inhibit the passage of current. MST will reportedly allow spintronic devices to operate at room temperature, creating devices like magnetic memory that operate hundreds of times faster than present technologies, turning even Moore's Law on its head.

Look for Mears Technologies, whose American headquarters is in Waltham, Massachusetts, to shortly announce its first licensee, which will likely be a fab plant in Asia.

Now what does all this mean for you and me? It means Moore's Law will remain in effect for at least another 15 years, which is long enough for most of those scary predictions of Ray Kurzweil to come true. You know, predictions like desktop computers with 10,000 times the processing power of my brain.

Though if you put it that way, maybe it's not so impressive after all.

Comments from the Tribe

Status: [CLOSED] read all comments (83)

Hi - Nice article. It might be more helpful to think about the current rather than the voltage though. If you are using a bucket of electrons to represent a digit, then increasing the clock speed means that you need to empty and fill the bucket faster. This means more current, and you are then hit by the heat being proportional to I^2R, the current squared times the resistance. Note that it is the current SQUARED. Lowering the voltage means that you can use smaller buckets, and also means that there will be less leakage as you say.



steve welch | Jan 31, 2008 | 8:46AM

clock speed and current are all the same
low heat and dollars the name of the game
MST wafers are cool and juicy
Mears and his team have done it you'll see

lord lucan | Jan 31, 2008 | 1:20PM

If the Mears team can deliver their multi adoptional technology then why isn't the industry rushing to impliment it NOW

Roy Giddis | Jan 31, 2008 | 3:26PM